library verilog;
use verilog.vl_types.all;
entity alu is
    generic(
        ADD             : vl_logic_vector(0 to 1) := (Hi0, Hi0);
        SUB             : vl_logic_vector(0 to 1) := (Hi0, Hi1);
        \OR\            : vl_logic_vector(0 to 1) := (Hi1, Hi0);
        \AND\           : vl_logic_vector(0 to 1) := (Hi1, Hi1)
    );
    port(
        busA            : in     vl_logic_vector(31 downto 0);
        busB            : in     vl_logic_vector(31 downto 0);
        ALUctr          : in     vl_logic_vector(1 downto 0);
        zero            : out    vl_logic_vector(31 downto 0);
        Alu_out         : out    vl_logic_vector(31 downto 0);
        Addr            : out    vl_logic_vector(31 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of ADD : constant is 1;
    attribute mti_svvh_generic_type of SUB : constant is 1;
    attribute mti_svvh_generic_type of \OR\ : constant is 1;
    attribute mti_svvh_generic_type of \AND\ : constant is 1;
end alu;
